A wide variety of implantable medical devices (IMDs) that employ electronic circuitry for providing electrical stimulation of body tissue and/or monitoring a physiologic condition are known in the art. A number of IMDs of various types deliver electrical stimulating pulses to selected body tissue and typically comprise an implantable pulse generator (IPG) for generating the stimulating pulses under prescribed conditions and at least one lead bearing a stimulation electrode for delivering the stimulating pulses to the selected tissue. For example, cardiac pacemakers and implantable cardioverter/defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of malignant tachyarrhythmias. Other IMDs have been developed for applying electrical stimulation or other therapies, e.g., drugs, to nerves, the brain, muscle groups and other organs and body tissues for treating a variety of conditions.
The earliest IPGs employed very simple analog circuit oscillators formed by discrete transistors and other circuit components and were very short-lived and electrically inefficient. Integrated circuit (IC) technology and battery improvements were made that enabled hermetic sealing of IMD housings, improved reliability and lengthened the operating life of the IMD. Improvements to the early IPGs included incorporation of an analog IC with digital IC into an operating system architecture providing an array of sophisticated operating functions, programmability of operating modes and parameters, data storage, and uplink telemetry functions. Successive generations of IMDs of this type have incorporated increased operating modes and functions through further improvements in circuitry and long-lived, low current output, low voltage batteries. Most recently, a wide number of IMD system architectures have been developed that incorporate custom microcomputers comprising a microprocessor, RAM and ROM, bus, and related elements of a typical microcomputer and other control logic, memory, input signal processing circuitry and therapy delivery output circuitry. The complexity of the circuitry, the functions provided, the longevity, and the reliability of the IMDs have all increased dramatically while the IMD size has decreased.
Current IMD operating system architectures typically are embodied in one or more IC(s) and discrete components mounted to one (or more) substrate employing hybrid fabrication circuitry techniques. The ICs may include one or more circuit blocks, each of which includes a plurality of circuitry components. Certain of the circuitry components on a particular IC perform analog or digital functions, input signal processing, and output therapy delivery. Digital logic ICs or circuitry are formed employing complementary metal oxide semiconductor (CMOS) fabrication technology. The digital logic ICs perform signal processing, timing, and state change functions embodying Boolean logic timed synchronously by a system-wide clock.
Even with these improvements, such digital logic ICs including those assembled from various clocked components such as logic gates, flip-flops, latches, and other Boolean logic blocks used in IMD system architectures suffer from several limitations and disadvantages. It is necessary to route clock distribution over the complete IC chip area as a clock tree of discrete electrical conductors or lines to reach all clocked components. The clock tree takes up IC chip real estate that could be used to increase device functions or memory capacity, dissipates power as heat, and increases overall power drain of the IC, decreasing useful life of the IMD battery. The clock tree also requires complex timing analysis and worst case design analysis and simulation to ensure design integrity because of possible clock skew and the resultant timing errors induced by race conditions. It would be desirable to minimize the use of IC real estate occupied by the clock tree, to simplify design analysis and simulation of the IMD system architecture and to decrease power consumption while increasing and improving processing capabilities of such IMDs.